{"title":"MBIST设计并实现了一个H.264/AVC视频解码器芯片","authors":"L. Hou, Wu-chen Wu, Jiahui Zhu","doi":"10.1109/ICSPS.2010.5555519","DOIUrl":null,"url":null,"abstract":"This paper implemented MBIST in a H.264/AVC video decoder chip, Neptune. Neptune has 1.5 million gates, 37 memory blocks. In need of testing, a complete design for test should be done. This paper mainly designed and implemented Memory BIST targeting the 34 RAM block, except the 3 ROM blocks. The design included building design flow, choosing algorithm, generating background data and BIST controller integration. By BIST controller reuse, circuit area was saved. Working mode simulation, test time analysis, fault coverage analysis, circuit performance evaluation were done. The result showed that the MBIST achieved 100% fault coverage by a 2.49% increase in chip area.","PeriodicalId":234084,"journal":{"name":"2010 2nd International Conference on Signal Processing Systems","volume":"47 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"MBIST design and implementation of a H.264/AVC video decoder chip\",\"authors\":\"L. Hou, Wu-chen Wu, Jiahui Zhu\",\"doi\":\"10.1109/ICSPS.2010.5555519\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper implemented MBIST in a H.264/AVC video decoder chip, Neptune. Neptune has 1.5 million gates, 37 memory blocks. In need of testing, a complete design for test should be done. This paper mainly designed and implemented Memory BIST targeting the 34 RAM block, except the 3 ROM blocks. The design included building design flow, choosing algorithm, generating background data and BIST controller integration. By BIST controller reuse, circuit area was saved. Working mode simulation, test time analysis, fault coverage analysis, circuit performance evaluation were done. The result showed that the MBIST achieved 100% fault coverage by a 2.49% increase in chip area.\",\"PeriodicalId\":234084,\"journal\":{\"name\":\"2010 2nd International Conference on Signal Processing Systems\",\"volume\":\"47 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-07-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 2nd International Conference on Signal Processing Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICSPS.2010.5555519\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 2nd International Conference on Signal Processing Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSPS.2010.5555519","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
MBIST design and implementation of a H.264/AVC video decoder chip
This paper implemented MBIST in a H.264/AVC video decoder chip, Neptune. Neptune has 1.5 million gates, 37 memory blocks. In need of testing, a complete design for test should be done. This paper mainly designed and implemented Memory BIST targeting the 34 RAM block, except the 3 ROM blocks. The design included building design flow, choosing algorithm, generating background data and BIST controller integration. By BIST controller reuse, circuit area was saved. Working mode simulation, test time analysis, fault coverage analysis, circuit performance evaluation were done. The result showed that the MBIST achieved 100% fault coverage by a 2.49% increase in chip area.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
