{"title":"1Mbit随机存取存储器的设计以取代eFlash","authors":"W. Diels, Alexander Standaert","doi":"10.1109/EUROCON.2015.7313804","DOIUrl":null,"url":null,"abstract":"A 1Mbit RRAM memory robust against variations in 45nm technology is presented. The focus lies on read reliability. To overcome variability a tuned reference signal is generated by connecting multiple reference cells in parallel. A bitline load has been designed to obtain maximum bitline voltage difference. Sense amplifier performance has been improved by allowing overlap between passgate-enable and latch-enable signals, this overlap gives rise to a nonlinear phenomenon, the RC-latch-effect. Write operation has not been included in the design and the results are based on circuit simulations.","PeriodicalId":133824,"journal":{"name":"IEEE EUROCON 2015 - International Conference on Computer as a Tool (EUROCON)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Design of 1Mbit RRAM memory to replace eFlash\",\"authors\":\"W. Diels, Alexander Standaert\",\"doi\":\"10.1109/EUROCON.2015.7313804\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 1Mbit RRAM memory robust against variations in 45nm technology is presented. The focus lies on read reliability. To overcome variability a tuned reference signal is generated by connecting multiple reference cells in parallel. A bitline load has been designed to obtain maximum bitline voltage difference. Sense amplifier performance has been improved by allowing overlap between passgate-enable and latch-enable signals, this overlap gives rise to a nonlinear phenomenon, the RC-latch-effect. Write operation has not been included in the design and the results are based on circuit simulations.\",\"PeriodicalId\":133824,\"journal\":{\"name\":\"IEEE EUROCON 2015 - International Conference on Computer as a Tool (EUROCON)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-11-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE EUROCON 2015 - International Conference on Computer as a Tool (EUROCON)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EUROCON.2015.7313804\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE EUROCON 2015 - International Conference on Computer as a Tool (EUROCON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EUROCON.2015.7313804","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 1Mbit RRAM memory robust against variations in 45nm technology is presented. The focus lies on read reliability. To overcome variability a tuned reference signal is generated by connecting multiple reference cells in parallel. A bitline load has been designed to obtain maximum bitline voltage difference. Sense amplifier performance has been improved by allowing overlap between passgate-enable and latch-enable signals, this overlap gives rise to a nonlinear phenomenon, the RC-latch-effect. Write operation has not been included in the design and the results are based on circuit simulations.
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