{"title":"具有多个感兴趣区域的图像应用的多访问存储器体系结构","authors":"Jinbo Xu, Y. Dou, Jie Zhou","doi":"10.1109/APCCAS.2008.4746335","DOIUrl":null,"url":null,"abstract":"We propose an efficient multi-access memory architecture for image applications with multiple interested regions. Conflict-free parallel access of randomly aligned rectangular blocks of data in the interested regions is achieved. Only interested regions in the image are transmitted from main memory to a secondary multi-module memory structure proposed in our work, and overlapped data between different regions are reused without retransfer. The addressing of data is not based on traditional predetermined addressing function, but based on a proposed table structure which maps virtual addresses to physical addresses of secondary memory modules. Synthesis results of our design on FPGA indicate that transfer speedups from 5.5 up to 32.9 in our experiments are achieved when compared with the scheme that accesses main memory directly.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Multi-access memory architecture for image applications with multiple interested regions\",\"authors\":\"Jinbo Xu, Y. Dou, Jie Zhou\",\"doi\":\"10.1109/APCCAS.2008.4746335\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We propose an efficient multi-access memory architecture for image applications with multiple interested regions. Conflict-free parallel access of randomly aligned rectangular blocks of data in the interested regions is achieved. Only interested regions in the image are transmitted from main memory to a secondary multi-module memory structure proposed in our work, and overlapped data between different regions are reused without retransfer. The addressing of data is not based on traditional predetermined addressing function, but based on a proposed table structure which maps virtual addresses to physical addresses of secondary memory modules. Synthesis results of our design on FPGA indicate that transfer speedups from 5.5 up to 32.9 in our experiments are achieved when compared with the scheme that accesses main memory directly.\",\"PeriodicalId\":344917,\"journal\":{\"name\":\"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APCCAS.2008.4746335\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS.2008.4746335","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Multi-access memory architecture for image applications with multiple interested regions
We propose an efficient multi-access memory architecture for image applications with multiple interested regions. Conflict-free parallel access of randomly aligned rectangular blocks of data in the interested regions is achieved. Only interested regions in the image are transmitted from main memory to a secondary multi-module memory structure proposed in our work, and overlapped data between different regions are reused without retransfer. The addressing of data is not based on traditional predetermined addressing function, but based on a proposed table structure which maps virtual addresses to physical addresses of secondary memory modules. Synthesis results of our design on FPGA indicate that transfer speedups from 5.5 up to 32.9 in our experiments are achieved when compared with the scheme that accesses main memory directly.