Dipanjan Sen, Savio Jay Sengupta, Subhashis Roy, Sudhabindu Ray, S. Sarkar
{"title":"双材料双栅无氧化堆结MOSFET在RFID存储单元实现中的影响分析","authors":"Dipanjan Sen, Savio Jay Sengupta, Subhashis Roy, Sudhabindu Ray, S. Sarkar","doi":"10.1109/DEVIC.2019.8783330","DOIUrl":null,"url":null,"abstract":"In this proposed article, a realization of RFID memory cell has been performed using Dual Material Double Gate Stack-Oxide Junction-Less MOSFET for high speed and low power application [1] in Sub-threshold regime. SNM, Power and Delay of the Memory Cell or SRAM circuit in different operating modes have been analyzed in depth. Dual Material Double Gate Oxide-Stack Junction-Less MOSFET (DMDGS-JLT) shows promising $\\mathrm{I}_\\mathrm{ON}/\\mathrm{I}_\\mathrm{OFF}$ ratio, less subthreshold swing and less Drain Induced Barrier Lowering or DIBL, in comparison with Double Gate Junction-Less MOSFET. So, proposed SRAM cell would be efficacious to offer less power dissipation and higher speed and a better Static Noise Margin. The impact of DMDGS-JLT in realizing RFID memory cell or SRAM has been studied in sub-threshold regime for ultra-low power tag design. Extensive simulations are performed using SILVACO ATLAS platform to validate the analyzed models. Besides, an optimum supply voltage range has been chosen to get an ultra-low power and higher speed of operation. DMDGS-JLT can be an alternative for ultra-low power Passive-RFID tag design, which results into greater time-span of the battery.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Impact Analysis of Dual Material Double Gate Oxide-Stack Junction-Less MOSFET in RFID Memory Cell Realisation\",\"authors\":\"Dipanjan Sen, Savio Jay Sengupta, Subhashis Roy, Sudhabindu Ray, S. Sarkar\",\"doi\":\"10.1109/DEVIC.2019.8783330\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this proposed article, a realization of RFID memory cell has been performed using Dual Material Double Gate Stack-Oxide Junction-Less MOSFET for high speed and low power application [1] in Sub-threshold regime. SNM, Power and Delay of the Memory Cell or SRAM circuit in different operating modes have been analyzed in depth. Dual Material Double Gate Oxide-Stack Junction-Less MOSFET (DMDGS-JLT) shows promising $\\\\mathrm{I}_\\\\mathrm{ON}/\\\\mathrm{I}_\\\\mathrm{OFF}$ ratio, less subthreshold swing and less Drain Induced Barrier Lowering or DIBL, in comparison with Double Gate Junction-Less MOSFET. So, proposed SRAM cell would be efficacious to offer less power dissipation and higher speed and a better Static Noise Margin. The impact of DMDGS-JLT in realizing RFID memory cell or SRAM has been studied in sub-threshold regime for ultra-low power tag design. Extensive simulations are performed using SILVACO ATLAS platform to validate the analyzed models. Besides, an optimum supply voltage range has been chosen to get an ultra-low power and higher speed of operation. DMDGS-JLT can be an alternative for ultra-low power Passive-RFID tag design, which results into greater time-span of the battery.\",\"PeriodicalId\":294095,\"journal\":{\"name\":\"2019 Devices for Integrated Circuit (DevIC)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 Devices for Integrated Circuit (DevIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DEVIC.2019.8783330\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Devices for Integrated Circuit (DevIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DEVIC.2019.8783330","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Impact Analysis of Dual Material Double Gate Oxide-Stack Junction-Less MOSFET in RFID Memory Cell Realisation
In this proposed article, a realization of RFID memory cell has been performed using Dual Material Double Gate Stack-Oxide Junction-Less MOSFET for high speed and low power application [1] in Sub-threshold regime. SNM, Power and Delay of the Memory Cell or SRAM circuit in different operating modes have been analyzed in depth. Dual Material Double Gate Oxide-Stack Junction-Less MOSFET (DMDGS-JLT) shows promising $\mathrm{I}_\mathrm{ON}/\mathrm{I}_\mathrm{OFF}$ ratio, less subthreshold swing and less Drain Induced Barrier Lowering or DIBL, in comparison with Double Gate Junction-Less MOSFET. So, proposed SRAM cell would be efficacious to offer less power dissipation and higher speed and a better Static Noise Margin. The impact of DMDGS-JLT in realizing RFID memory cell or SRAM has been studied in sub-threshold regime for ultra-low power tag design. Extensive simulations are performed using SILVACO ATLAS platform to validate the analyzed models. Besides, an optimum supply voltage range has been chosen to get an ultra-low power and higher speed of operation. DMDGS-JLT can be an alternative for ultra-low power Passive-RFID tag design, which results into greater time-span of the battery.