FPGA-based stereo vision hardware for generating dense disparity maps

We propose a stereo vision hardware solution for image matching in real-time. Previous systems use dedicated special-purpose hardware and report different results in terms of performance, cost and quality. This work aims to build a library of hardware components for stereo vision systems, which can be ported to different architectures implemented in FPGA. Some modules were optimized in terms of FPGA resources used inside the chip. Meanwhile the ratio between the clock rate obtained for each component and the maximum frequency allowed by the FPGA was improved. We also introduce a multi-cycle pipeline implementation for SAD-based image matching, which facilitates a trade-off between chip area usage and operating speed.