Robust design of deep Sub-micron CMOS wireless SoC

Scaled CMOS technology has opened the door of CMOS wireless SoC. The bright side is, apparently, high integration level and low cost implementation brought by the huge capacity of standard CMOS. However, as a designer point of view, another side should also be addressed, especially on PVT variation issues of scaled CMOS. In this paper, we will show the issues and their respective countermeasures on a voltage controlled oscillator in the local oscillator, a low noise amplifier and a channel select filter in the receiver, and digital calibration of I/Q mismatch in the transmitter.