{"title":"具有运行时可配置参数的多数据流的灵活实时立体视觉体系结构","authors":"Zhaoteng Meng, L. Shu, Jie Hao","doi":"10.1109/FPL57034.2022.00024","DOIUrl":null,"url":null,"abstract":"It is significant for a stereo vision real-time computing system to flexibly adapt to different parameters of stereo matching without re-customizing hardwares. In this paper, a configurable pipelined hardware architecture based on the sum of absolute differences (SAD) algorithm is proposed. We split the SAD calculation into two parts to accommodate pipelined computing. The architecture can be configured with different resolutions, window sizes, and disparity levels without stopping and restarting. In addition, it can be configured as a multiple-data-stream mode and we have developed a configuration gen-eration algorithm for the mode. The presented architecture is synthesized and implemented on a Xilinx ZCUI04 board. The evaluation results demonstrate that the real-time computing of 480P, 720P, and 1080P video streams can be process at 250MHz with the peak computing performance of 480P/784fps at the disparity level of 125. It uses 60% LUTs, 34% registers, and 39 % BRAM, producing flexible configurability and superior computing performance than the other similar work.","PeriodicalId":380116,"journal":{"name":"2022 32nd International Conference on Field-Programmable Logic and Applications (FPL)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Flexible Real-Time Stereo Vision Architecture for Multiple Data Streams with Runtime Configurable Parameters\",\"authors\":\"Zhaoteng Meng, L. Shu, Jie Hao\",\"doi\":\"10.1109/FPL57034.2022.00024\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"It is significant for a stereo vision real-time computing system to flexibly adapt to different parameters of stereo matching without re-customizing hardwares. In this paper, a configurable pipelined hardware architecture based on the sum of absolute differences (SAD) algorithm is proposed. We split the SAD calculation into two parts to accommodate pipelined computing. The architecture can be configured with different resolutions, window sizes, and disparity levels without stopping and restarting. In addition, it can be configured as a multiple-data-stream mode and we have developed a configuration gen-eration algorithm for the mode. The presented architecture is synthesized and implemented on a Xilinx ZCUI04 board. The evaluation results demonstrate that the real-time computing of 480P, 720P, and 1080P video streams can be process at 250MHz with the peak computing performance of 480P/784fps at the disparity level of 125. It uses 60% LUTs, 34% registers, and 39 % BRAM, producing flexible configurability and superior computing performance than the other similar work.\",\"PeriodicalId\":380116,\"journal\":{\"name\":\"2022 32nd International Conference on Field-Programmable Logic and Applications (FPL)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 32nd International Conference on Field-Programmable Logic and Applications (FPL)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/FPL57034.2022.00024\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 32nd International Conference on Field-Programmable Logic and Applications (FPL)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/FPL57034.2022.00024","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Flexible Real-Time Stereo Vision Architecture for Multiple Data Streams with Runtime Configurable Parameters
It is significant for a stereo vision real-time computing system to flexibly adapt to different parameters of stereo matching without re-customizing hardwares. In this paper, a configurable pipelined hardware architecture based on the sum of absolute differences (SAD) algorithm is proposed. We split the SAD calculation into two parts to accommodate pipelined computing. The architecture can be configured with different resolutions, window sizes, and disparity levels without stopping and restarting. In addition, it can be configured as a multiple-data-stream mode and we have developed a configuration gen-eration algorithm for the mode. The presented architecture is synthesized and implemented on a Xilinx ZCUI04 board. The evaluation results demonstrate that the real-time computing of 480P, 720P, and 1080P video streams can be process at 250MHz with the peak computing performance of 480P/784fps at the disparity level of 125. It uses 60% LUTs, 34% registers, and 39 % BRAM, producing flexible configurability and superior computing performance than the other similar work.