下一代64字节安腾微处理器上的16 kB单周期读访问缓存

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI:10.1109/ISSCC.2002.992963

D. Bradley, P. Mahoney, B. Stackhouse

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引用次数: 21

摘要

放置在64字节安腾微处理器上的16 kB四端口物理寻址缓存工作在1.2 GHz，峰值带宽为19.2 GB/s。电路和微架构技术进行了优化，以允许单周期读访问延迟。在0.18 μm CMOS工艺中，缓存占用3.2×1.8 mm/sup 2/。

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The 16 kB single-cycle read access cache on a next-generation 64 b Itanium microprocessor

A 16 kB four-ported physically addressed cache to be placed on a 64 b Itanium microprocessor operates at 1.2 GHz with 19.2 GB/s peak bandwidth. Circuit and microarchitectural techniques are optimized to allow a single-cycle read access latency. The cache occupies 3.2×1.8 mm/sup 2/ in a 0.18 μm CMOS process.

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2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

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