Time-Interleaved Polyphase Decimation Filter Using Signed-Digit Adders

Decimation filters for high-speed oversampling delta-sigma converters have been investigated by using signed-digit adders. Time-interleaved technique is introduced to a polyphase FIR filter to overcome operation speed limitation due to the setup and hold time constraint for delayed flip-flops. It is found that in this architecture, the adder tree based on ternary signed-digit full adders effectively improves the operation speed. A third-order filters with a decimation factor of 8 is designed by assuming a 0.18-μm standard CMOS technology. Signal-levelsimulation shows that the operation frequency of the present time-interleaved filter is improved by 20% compared withconventional polyphase filters.