下一代逻辑寻径的智能DTCO (iDTCO)

2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) Pub Date : 2018-09-01 DOI:10.1109/SISPAD.2018.8551723

U. Kwon, T. Okagaki, Young-seok Song, Sungyeol Kim, Yohan Kim, Minkyoung Kim, A. Kim, Saetbyeol Ahn, Jihye Shin, Yonghee Park, Jongchol Kim, D. Kim, Weiyi Qi, Yang Lu, Nuo Xu, Hong-hyun Park, J. Wang, W. Choi

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引用次数: 0

摘要

介绍了下一代逻辑体系结构寻路的智能设计技术协同优化方法及其应用效果。我们的iDTCO框架有两个主要步骤;标准单元(STC)级iDTCO和块级iDTCO。本文主要研究的stc级iDTCO由4个主要组成部分组成;(1)采用标准电池(STC)布局的光刻轮廓进行全三维工艺仿真;(2)晶体管紧凑模型的自动提取与三维寄生RC提取(PEX);(3)性能功率产率(PPY)分析仪;(4)布局与工艺假设(PA)的多目标优化以获得最佳PPY。将我们的stc级iDTCO流应用于逻辑arch寻径，我们可以将我们的PPY分析TAT速度提高5$\sim$10倍，准确率>95%。

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Intelligent DTCO (iDTCO) for next generation logic path-finding

Intelligent design technology co-optimization (iDTCO) methodology for next generation logic architecture pathfinding and its application results are presented in this paper. There are 2 major steps in our iDTCO framework; standard cell (STC)-level iDTCO and block-level iDTCO. STC-level iDTCO, the main focus of this paper, consists of 4 major components; (1) full 3D process emulation with litho contour of standard cell (STC) layout, (2) auto-extraction of transistor compact model & parasitic RC extraction (PEX) in 3D, (3) performance-power-yield (PPY) analyzer, (4) multi-objective optimization of layout & process assumption (PA) to get best PPY. Applying our STC-level iDTCO flow to logic arch pathfinding, we could speed up our PPY analysis TAT by 5$\sim$10 times with good accuracy of >95%.

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2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

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