Implementation of DBFN processor for Synthetic Aperture Radar application

One of the main reasons why Synthetic Aperture Radar (SAR) is an attractive solution for earth surface screening applications is its reliability independent on the weather conditions. This paper presents the implementation details of digital beamforming baseband core processor for such a SAR system. The processor chip is part of a distributed beamforming network (DBFN) of 16 baseband processors where each one processes data obtained from four 210MSPS ADC cores. Due to requirements related to space environment, the baseband is implemented in radiation-tolerant manner in order to temper single event effects (SEE). Instead of full-chip protection, the baseband processor uses only partially radhard flip-flops. This trade-off saves 25.87 % of silicon area based on gate-level synthesis results. A prototype is produced in a low-cost variant of a 0.25 μm BiCMOS process. First measurement results show an average operating current of 445.49 mA at a clock speed of 210 MHz and a 2.5 V power supply.