LVCMOS I/O standard based million MHz high performance energy efficient design on FPGA

In design and implementation of energy efficient counter for energy efficient processor, we are using LVCMOS I/O standard in FPGA. CMOS technology is used to achieve energy efficiency with corresponding low voltage. We observe that when counter operates at 1×106MHz device operating frequency, there is 67.42% reduction in clock power and 75.99% reduction in IO power with LVCMOS I/O Standard. In counter, we are using numbers of flip-flops and register. In this whole work, we are using three different classes of LVCMOS namely LVCMOS15, LVCMOS18 and LVCMOS33. When counter is operating at 1000MHz, the reduction in I/O power requirement of LVCMOS18 is 67.63% and of LVCMOS15 is 75.72% as compared to LVCMOS33. When frame buffer is operating at 10000MHz, the reduction in I/O power requirement of LVCMOS18 is 67.45% and of LVCMOS15 is 75.99% as compared to LVCMOS33. When frame buffer is operating at 100000MHz, there is 67.42% reduction in clock power and 75.99% reduction in IO power with LVCMOS I/O Standard. Other component of dynamic power like Clock power, Logic power and Signal power are independent of I/O standard. This implimentation is made on 28nm 7 Series Kintex-7 (7k70tfbg676-3) FPGA.