UART Implementation using the BIST Technique for Generating Test Patterns

The rapid development of technology had reflected in the shrinking and complexity of VLSI circuits. Designers of such complex circuits must prioritize testability to guarantee the circuits' longevity and functionality. Sub-micron technological development increased the difficulty of testing VLSI circuits, requiring the hunt for alternatives to traditional testing. BIST is helpful because it allows the Test Pattern Generator (TPG) as well as Response Analyzer to assess modules without separating them from underlying circuits. The Universal Asynchronous Receiver Transmitter (UART) is used mainly for short-distance communication between CPUs and peripherals. Our aim is to develop a BIST-compliant UART. We designed an eight-bit UART module that may be utilized in two modes: testing and normal operation. The experiments were carried out with the help of a Linear Feedback Shift Register (LFSR) as well as a Multiple Input Signature Register (MISR). This article describes how to create a UART with BIST capabilities in Verilog HDL, which is subsequently simulated in Xilinx Vivado.