{"title":"硬件系统的符号验证","authors":"H. Barringer, G. Gough, B. Monahan, A. Williams","doi":"10.1109/ASPDAC.1995.486380","DOIUrl":null,"url":null,"abstract":"We describe a method for verifying the behavioural equivalence of hardware systems, modelled as deterministic machines, based on the symbolic simulation of the two systems. The state evolution method compares the behaviour of systems at an abstract level, and reduces the problem of checking the behavioural equivalence to one of needing to prove that a set of logical verification conditions are valid. The approach maintains a high degree of automation while offering the possibility of containing the usual growth in complexity of verification, and can be applied to certain systems which have infinite state-spaces.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Symbolic verification of hardware systems\",\"authors\":\"H. Barringer, G. Gough, B. Monahan, A. Williams\",\"doi\":\"10.1109/ASPDAC.1995.486380\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We describe a method for verifying the behavioural equivalence of hardware systems, modelled as deterministic machines, based on the symbolic simulation of the two systems. The state evolution method compares the behaviour of systems at an abstract level, and reduces the problem of checking the behavioural equivalence to one of needing to prove that a set of logical verification conditions are valid. The approach maintains a high degree of automation while offering the possibility of containing the usual growth in complexity of verification, and can be applied to certain systems which have infinite state-spaces.\",\"PeriodicalId\":119232,\"journal\":{\"name\":\"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair\",\"volume\":\"17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-08-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASPDAC.1995.486380\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASPDAC.1995.486380","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
We describe a method for verifying the behavioural equivalence of hardware systems, modelled as deterministic machines, based on the symbolic simulation of the two systems. The state evolution method compares the behaviour of systems at an abstract level, and reduces the problem of checking the behavioural equivalence to one of needing to prove that a set of logical verification conditions are valid. The approach maintains a high degree of automation while offering the possibility of containing the usual growth in complexity of verification, and can be applied to certain systems which have infinite state-spaces.
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