Memory Encryption Support for an FPGA-based RISC-V Implementation

Security is an important driver for the evolution of the RISC-V architecture. Several initiatives aim at exploiting the privileged architecture and the Physical Memory Protection mechanisms foreseen by the RISC-V specification as a foundation for robust trusted execution environments. This short paper introduces a memory encryption unit fitting the organization of the RISC-V privileged architecture. The unit is suitable for very resource-constrained systems and is mainly targeted at FPGA devices. The design relies on a flexible and efficient stream cipher, the ChaCha algorithm. The work presents an overview of the system architecture and the detail of the FPGA-based implementation of the memory encryption unit, along with some experimental evaluation and comparisons with state-of-the-art contributions.