{"title":"40gb /s网络数据流处理","authors":"Jiri Halak, S. Ubik, P. Zejdl","doi":"10.1109/ICDT.2010.35","DOIUrl":null,"url":null,"abstract":"For emerging 40 Gb/s computer networks, we need devices that are capable of sustained line-rate operation for monitoring, test patterns generation and data stream processing. In this paper, we describe design options and our practical experience with developing such a platform for 40 Gb/s network. We present a working prototype for 40 Gb/s networks using SERDES Framer Interface Level 5 (SFI-5) communication protocol and prove that high speed network processing such as 40 Gb/s lines is possible with embedded system using an FPGA device.","PeriodicalId":322589,"journal":{"name":"2010 Fifth International Conference on Digital Telecommunications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Data Stream Processing for 40 Gb/s Networks\",\"authors\":\"Jiri Halak, S. Ubik, P. Zejdl\",\"doi\":\"10.1109/ICDT.2010.35\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"For emerging 40 Gb/s computer networks, we need devices that are capable of sustained line-rate operation for monitoring, test patterns generation and data stream processing. In this paper, we describe design options and our practical experience with developing such a platform for 40 Gb/s network. We present a working prototype for 40 Gb/s networks using SERDES Framer Interface Level 5 (SFI-5) communication protocol and prove that high speed network processing such as 40 Gb/s lines is possible with embedded system using an FPGA device.\",\"PeriodicalId\":322589,\"journal\":{\"name\":\"2010 Fifth International Conference on Digital Telecommunications\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 Fifth International Conference on Digital Telecommunications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICDT.2010.35\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 Fifth International Conference on Digital Telecommunications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICDT.2010.35","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
For emerging 40 Gb/s computer networks, we need devices that are capable of sustained line-rate operation for monitoring, test patterns generation and data stream processing. In this paper, we describe design options and our practical experience with developing such a platform for 40 Gb/s network. We present a working prototype for 40 Gb/s networks using SERDES Framer Interface Level 5 (SFI-5) communication protocol and prove that high speed network processing such as 40 Gb/s lines is possible with embedded system using an FPGA device.
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