{"title":"整数平方根的VLSI算法","authors":"N. Takagi, K. Takagi","doi":"10.1109/ISPACS.2006.364734","DOIUrl":null,"url":null,"abstract":"A VLSI algorithm for integer square-rooting is proposed. It is based on the radix-2 non-restoring square-rooting algorithm. Fast computation is achieved by the use of the radix-2 signed-digit representation. Nonetheless, the algorithm does not require normalization of the operand. Combinational (unfolded) implementation of the algorithm yields a regularly structured array square-rooter. Its delay is proportional to n, the bit length of the operand, while that of conventional ones is at least proportional to n log n.","PeriodicalId":178644,"journal":{"name":"2006 International Symposium on Intelligent Signal Processing and Communications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"A VLSI Algorithm for Integer Square-Rooting\",\"authors\":\"N. Takagi, K. Takagi\",\"doi\":\"10.1109/ISPACS.2006.364734\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A VLSI algorithm for integer square-rooting is proposed. It is based on the radix-2 non-restoring square-rooting algorithm. Fast computation is achieved by the use of the radix-2 signed-digit representation. Nonetheless, the algorithm does not require normalization of the operand. Combinational (unfolded) implementation of the algorithm yields a regularly structured array square-rooter. Its delay is proportional to n, the bit length of the operand, while that of conventional ones is at least proportional to n log n.\",\"PeriodicalId\":178644,\"journal\":{\"name\":\"2006 International Symposium on Intelligent Signal Processing and Communications\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 International Symposium on Intelligent Signal Processing and Communications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISPACS.2006.364734\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 International Symposium on Intelligent Signal Processing and Communications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPACS.2006.364734","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A VLSI algorithm for integer square-rooting is proposed. It is based on the radix-2 non-restoring square-rooting algorithm. Fast computation is achieved by the use of the radix-2 signed-digit representation. Nonetheless, the algorithm does not require normalization of the operand. Combinational (unfolded) implementation of the algorithm yields a regularly structured array square-rooter. Its delay is proportional to n, the bit length of the operand, while that of conventional ones is at least proportional to n log n.