高性能轨对轨CMOS运放at /spl plusmn/3V电源的设计与仿真

Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06) Pub Date : 2006-01-17 DOI:10.1109/DELTA.2006.30

M. Bhaskaran, S. Sriram, A. Stojcevski, A. Zayegh

{"title":"高性能轨对轨CMOS运放at /spl plusmn/3V电源的设计与仿真","authors":"M. Bhaskaran, S. Sriram, A. Stojcevski, A. Zayegh","doi":"10.1109/DELTA.2006.30","DOIUrl":null,"url":null,"abstract":"The paper discusses a CMOS operational amplifier at /spl plusmn/ 3 V supply, with rail-to-rail input and output performance. The trade-off between rail-to-rail performance and power consumption, in terms of bias current is observed. Simulation results with SPICE Level 3 models, using cadence tools, are discussed and compared with other op-amps. The proposed circuit exhibits high speed with slew rate of 49.24 V//spl mu/s, better rejection ratios and offset performance, and consumes a power of 25.44 mW for rail-to-rail performance. The paper also discusses the effects of reducing the bias current to reduce power consumption.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Design and simulation of a high performance rail-to-rail CMOS op-amp at /spl plusmn/3V supply\",\"authors\":\"M. Bhaskaran, S. Sriram, A. Stojcevski, A. Zayegh\",\"doi\":\"10.1109/DELTA.2006.30\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper discusses a CMOS operational amplifier at /spl plusmn/ 3 V supply, with rail-to-rail input and output performance. The trade-off between rail-to-rail performance and power consumption, in terms of bias current is observed. Simulation results with SPICE Level 3 models, using cadence tools, are discussed and compared with other op-amps. The proposed circuit exhibits high speed with slew rate of 49.24 V//spl mu/s, better rejection ratios and offset performance, and consumes a power of 25.44 mW for rail-to-rail performance. The paper also discusses the effects of reducing the bias current to reduce power consumption.\",\"PeriodicalId\":439448,\"journal\":{\"name\":\"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-01-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DELTA.2006.30\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DELTA.2006.30","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

摘要

本文讨论了一种具有轨对轨输入和输出性能的/spl plusmn/ 3v供电的CMOS运算放大器。在偏置电流方面，观察到轨对轨性能和功耗之间的权衡。讨论了SPICE 3级模型的仿真结果，并与其他运放进行了比较。该电路具有较高的速度，摆幅率为49.24 V//spl mu/s，具有较好的抑制比和失调性能，轨间性能功耗为25.44 mW。本文还讨论了减小偏置电流对降低功耗的影响。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Design and simulation of a high performance rail-to-rail CMOS op-amp at /spl plusmn/3V supply

The paper discusses a CMOS operational amplifier at /spl plusmn/ 3 V supply, with rail-to-rail input and output performance. The trade-off between rail-to-rail performance and power consumption, in terms of bias current is observed. Simulation results with SPICE Level 3 models, using cadence tools, are discussed and compared with other op-amps. The proposed circuit exhibits high speed with slew rate of 49.24 V//spl mu/s, better rejection ratios and offset performance, and consumes a power of 25.44 mW for rail-to-rail performance. The paper also discusses the effects of reducing the bias current to reduce power consumption.

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Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)

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