一种低漏电流功率180nm CMOS SRAM

2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI:10.1109/ASPDAC.2008.4483914

T. Enomoto, Yuki Higuchi

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引用次数: 10

摘要

制备了低漏功率180nm的1K-b SRAM。采用新开发的泄漏电流减小电路“自控电压电平(SVL)”电路的1k位存储单元阵列的待机泄漏功率仅为3.7 nW，是同等传统存储单元阵列在VDD为1.8 V时的5.4%。另一方面，速度几乎保持不变，内存单元阵列面积的开销最小。

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A low-leakage current power 180-nm CMOS SRAM

A low leakage power, 180-nm 1K-b SRAM was fabricated. The stand-by leakage power of a 1K-bit memory cell array incorporating a newly-developed leakage current reduction circuit called a "self-controllable voltage level (SVL)" circuit was only 3.7 nW, which is 5.4% that of an equivalent conventional memory-cell array at a VDD of 1.8 V. On the other hand, the speed remained almost constant with a minimal overhead in terms of the memory cell array area.

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2008 Asia and South Pacific Design Automation Conference

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