用双模通型晶体管逻辑实现高性能4位ALU

Anurag Chauhan, K. K. Saini, Nitin Rajput, Rushil Domah
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引用次数: 2

摘要

本文提出了一种采用双模通型晶体管逻辑实现的高效节能且温度不变的四位算术逻辑单元。采用CMOS逻辑和双模通管逻辑设计了NOR和NAND等基本逻辑门,并在本设计中使用。仿真结果表明,DMPL可使动态模式下的NOR和NAND门的最坏情况延迟分别降低42.39%和39.13%,静态模式下的NOR和NAND门的平均功耗分别降低67.96%和24.09%。在实现的算术和逻辑单元中,我们观察到最坏情况延迟和平均功耗分别降低了62.67%和28.28%。使用Cadence®Virtuoso®原理图编辑器在90nm批量技术中实现了所提出的逻辑。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Implementation of High Performance 4-Bit ALU using Dual Mode Pass Transistor Logic
In this paper, we present a four bit arithmetic logic unit which is energy efficient and temperature invariant implemented using the dual mode pass transistor logic. The basic logic gates such as NOR and NAND are designed using both CMOS logic and dual mode pass transistor logic and are used in the proposed design. Simulations performed demonstrated that DMPL can reduce the computed worst case delay by 42.39%and 39.13%for NOR and NAND gates respectively in dynamic mode and average power dissipation by 67.96%and 24.09%for NOR and NAND gates respectively in static mode. In the implemented Arithmetic and Logic Unit, we observe a reduction in worst case delay and average power dissipation by 62.67%and 28.28%. The proposed logic was implemented in 90nm bulk technology using Cadence® Virtuoso® Schematic Editor.
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