回顾GPGPU流架构的排序

D. Merrill, A. Grimshaw
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引用次数: 162

摘要

这张海报展示了使用GPGPU流处理器对固定长度键(和值)的大序列进行排序的有效策略。与最先进的技术相比,我们的基数排序方法在所有一代NVIDIA gpgpu上的速度至少提高了2倍,在当前基于gt200的模型上的速度最高可提高3.7倍。我们的实现演示了每秒4.82亿个键值对和每秒5.5亿个键(32位)的排序速率。对于这个排序问题领域,我们相信我们的排序原语是任何完全可编程的微体系结构中最快的。这些结果激发了GPGPU流架构的不同种类的并行原语,这些原语可以更好地利用内存和计算资源,同时保持可重用组件的灵活性。我们的排序性能来源于并行扫描流原语,该原语以两种方式进行了推广:(1)具有用于生产者/消费者操作(访问逻辑)的本地接口,以及(2)具有用于执行多个相关并发前缀扫描(多扫描)的接口。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Revisiting sorting for GPGPU stream architectures
This poster presents efficient strategies for sorting large sequences of fixed-length keys (and values) using GPGPU stream processors. Compared to the state-of-the-art, our radix sorting methods exhibit speedup of at least 2x for all generations of NVIDIA GPGPUs, and up to 3.7x for current GT200-based models. Our implementations demonstrate sorting rates of 482 million key-value pairs per second, and 550 million keys per second (32-bit). For this domain of sorting problems, we believe our sorting primitive to be the fastest available for any fully-programmable microarchitecture. These results motivate a different breed of parallel primitives for GPGPU stream architectures that can better exploit the memory and computational resources while maintaining the flexibility of a reusable component. Our sorting performance is derived from a parallel scan stream primitive that has been generalized in two ways: (1) with local interfaces for producer/consumer operations (visiting logic), and (2) with interfaces for performing multiple related, concurrent prefix scans (multi-scan).
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