数据预取机制的分类

S. Byna, Yong Chen, Xian-He Sun
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引用次数: 43

摘要

数据预取被认为是一种有效的方法来掩盖由缓存丢失引起的数据访问延迟,并弥合处理器和内存之间的性能差距。在硬件和/或软件的支持下,数据预取使数据在实际需要之前更接近处理器。在过去的几年中,已经提出了许多预取技术,通过利用多核架构来减少数据访问延迟。在本文中,我们提出了一种分类法,对开发预取策略时的各种设计关注点进行分类。我们讨论了在设计多核处理器的预取策略时必须考虑的各种预取策略和问题。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Taxonomy of Data Prefetching Mechanisms
Data prefetching has been considered an effective way to mask data access latency caused by cache misses and to bridge the performance gap between processor and memory. With hardware and/or software support, data prefetching brings data closer to a processor before it is actually needed. Many prefetching techniques have been proposed in the last few years to reduce data access latency by taking advantage of multi-core architectures. In this paper, we propose a taxonomy that classifies various design concerns in developing a prefetching strategy. We discuss various prefetching strategies and issues that have to be considered in designing a prefetching strategy for multi-core processors.
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