Imran Ali, Muhammad Asif, Y. Qaragoez, M. R. Rehman, Kangyoon Lee
{"title":"基于温度补偿的自适应PA调制指数控制器","authors":"Imran Ali, Muhammad Asif, Y. Qaragoez, M. R. Rehman, Kangyoon Lee","doi":"10.1109/ISOCC47750.2019.9078490","DOIUrl":null,"url":null,"abstract":"In this paper, an adaptive power amplifier (PA) modulation index controller with temperature compensation is presented for 5.8 GHz dedicated short-range communication (DSRC) transceiver applications. The number of Class-E type PA cores are configurable for amplitude shift keying (ASK) modulation and correction factor due to temperature variation is compensated adaptively in automatic mode to keep constant PA output power. In external mode, the modulation index and correction factor are configurable for the suitable number of core selection for higher PA output power. The design consumes 17.29 nW power and draws 14.41 nA current from 1.2 V supply. The proposed design is fully synthesizable and it needs only 854 gates for its implementation in 130 nm CMOS process with 64 × 153 μm² of area.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"An Adaptive PA Modulation Index Controller with Temperature Compensation for DSRC Applications\",\"authors\":\"Imran Ali, Muhammad Asif, Y. Qaragoez, M. R. Rehman, Kangyoon Lee\",\"doi\":\"10.1109/ISOCC47750.2019.9078490\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, an adaptive power amplifier (PA) modulation index controller with temperature compensation is presented for 5.8 GHz dedicated short-range communication (DSRC) transceiver applications. The number of Class-E type PA cores are configurable for amplitude shift keying (ASK) modulation and correction factor due to temperature variation is compensated adaptively in automatic mode to keep constant PA output power. In external mode, the modulation index and correction factor are configurable for the suitable number of core selection for higher PA output power. The design consumes 17.29 nW power and draws 14.41 nA current from 1.2 V supply. The proposed design is fully synthesizable and it needs only 854 gates for its implementation in 130 nm CMOS process with 64 × 153 μm² of area.\",\"PeriodicalId\":113802,\"journal\":{\"name\":\"2019 International SoC Design Conference (ISOCC)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-10-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 International SoC Design Conference (ISOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISOCC47750.2019.9078490\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 International SoC Design Conference (ISOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISOCC47750.2019.9078490","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An Adaptive PA Modulation Index Controller with Temperature Compensation for DSRC Applications
In this paper, an adaptive power amplifier (PA) modulation index controller with temperature compensation is presented for 5.8 GHz dedicated short-range communication (DSRC) transceiver applications. The number of Class-E type PA cores are configurable for amplitude shift keying (ASK) modulation and correction factor due to temperature variation is compensated adaptively in automatic mode to keep constant PA output power. In external mode, the modulation index and correction factor are configurable for the suitable number of core selection for higher PA output power. The design consumes 17.29 nW power and draws 14.41 nA current from 1.2 V supply. The proposed design is fully synthesizable and it needs only 854 gates for its implementation in 130 nm CMOS process with 64 × 153 μm² of area.