用于ECC处理器的可伸缩GF(2/sup m/)算术单元

W. Chelton, M. Benaissa
{"title":"用于ECC处理器的可伸缩GF(2/sup m/)算术单元","authors":"W. Chelton, M. Benaissa","doi":"10.1109/SIPS.2004.1363076","DOIUrl":null,"url":null,"abstract":"This paper proposes a new architecture for an arithmetic unit (AU) for applications that operate over GF(2/sup m/), in particular elliptic curve cryptography. The AU is completely scalable enabling it to operate over any field degree without the need to reconfigure hardware. Operands are considered as a series of w-bit words, where w can be set to meet design requirements. By transferring the complexity of control to software, whilst retaining the generic functions of division and multiplication in hardware, a low area, highly flexible implementation can be attained. A proof-of concept AU was implemented and tested in FPGA. Theoretical results were calculated for scalar multiplication, which were compared to a less scalable implementation. Though the AU cannot achieve the computational speed attained by the other implementation it offers potentially large improvements when considering the area-time product and, therefore, improved efficiency.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A scalable GF(2/sup m/) arithmetic unit for application in an ECC processor\",\"authors\":\"W. Chelton, M. Benaissa\",\"doi\":\"10.1109/SIPS.2004.1363076\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes a new architecture for an arithmetic unit (AU) for applications that operate over GF(2/sup m/), in particular elliptic curve cryptography. The AU is completely scalable enabling it to operate over any field degree without the need to reconfigure hardware. Operands are considered as a series of w-bit words, where w can be set to meet design requirements. By transferring the complexity of control to software, whilst retaining the generic functions of division and multiplication in hardware, a low area, highly flexible implementation can be attained. A proof-of concept AU was implemented and tested in FPGA. Theoretical results were calculated for scalar multiplication, which were compared to a less scalable implementation. Though the AU cannot achieve the computational speed attained by the other implementation it offers potentially large improvements when considering the area-time product and, therefore, improved efficiency.\",\"PeriodicalId\":384858,\"journal\":{\"name\":\"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-12-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SIPS.2004.1363076\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIPS.2004.1363076","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7

摘要

本文提出了一种新的算法单元(AU)体系结构,适用于GF(2/sup m/)上的应用,特别是椭圆曲线密码。AU是完全可扩展的,使其能够在任何领域的程度上运行,而无需重新配置硬件。操作数被认为是一系列w位的字,其中w可以设置以满足设计要求。通过将控制的复杂性转移到软件中,同时在硬件中保留除法和乘法的通用功能,可以实现低面积,高度灵活的实现。一个概念验证的AU在FPGA中实现和测试。计算了标量乘法的理论结果,并将其与可扩展性较低的实现进行了比较。虽然AU不能达到其他实现所达到的计算速度,但在考虑面积-时间乘积时,它提供了潜在的巨大改进,因此提高了效率。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A scalable GF(2/sup m/) arithmetic unit for application in an ECC processor
This paper proposes a new architecture for an arithmetic unit (AU) for applications that operate over GF(2/sup m/), in particular elliptic curve cryptography. The AU is completely scalable enabling it to operate over any field degree without the need to reconfigure hardware. Operands are considered as a series of w-bit words, where w can be set to meet design requirements. By transferring the complexity of control to software, whilst retaining the generic functions of division and multiplication in hardware, a low area, highly flexible implementation can be attained. A proof-of concept AU was implemented and tested in FPGA. Theoretical results were calculated for scalar multiplication, which were compared to a less scalable implementation. Though the AU cannot achieve the computational speed attained by the other implementation it offers potentially large improvements when considering the area-time product and, therefore, improved efficiency.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信