{"title":"用于ECC处理器的可伸缩GF(2/sup m/)算术单元","authors":"W. Chelton, M. Benaissa","doi":"10.1109/SIPS.2004.1363076","DOIUrl":null,"url":null,"abstract":"This paper proposes a new architecture for an arithmetic unit (AU) for applications that operate over GF(2/sup m/), in particular elliptic curve cryptography. The AU is completely scalable enabling it to operate over any field degree without the need to reconfigure hardware. Operands are considered as a series of w-bit words, where w can be set to meet design requirements. By transferring the complexity of control to software, whilst retaining the generic functions of division and multiplication in hardware, a low area, highly flexible implementation can be attained. A proof-of concept AU was implemented and tested in FPGA. Theoretical results were calculated for scalar multiplication, which were compared to a less scalable implementation. Though the AU cannot achieve the computational speed attained by the other implementation it offers potentially large improvements when considering the area-time product and, therefore, improved efficiency.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A scalable GF(2/sup m/) arithmetic unit for application in an ECC processor\",\"authors\":\"W. Chelton, M. Benaissa\",\"doi\":\"10.1109/SIPS.2004.1363076\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes a new architecture for an arithmetic unit (AU) for applications that operate over GF(2/sup m/), in particular elliptic curve cryptography. The AU is completely scalable enabling it to operate over any field degree without the need to reconfigure hardware. Operands are considered as a series of w-bit words, where w can be set to meet design requirements. By transferring the complexity of control to software, whilst retaining the generic functions of division and multiplication in hardware, a low area, highly flexible implementation can be attained. A proof-of concept AU was implemented and tested in FPGA. Theoretical results were calculated for scalar multiplication, which were compared to a less scalable implementation. Though the AU cannot achieve the computational speed attained by the other implementation it offers potentially large improvements when considering the area-time product and, therefore, improved efficiency.\",\"PeriodicalId\":384858,\"journal\":{\"name\":\"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-12-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SIPS.2004.1363076\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIPS.2004.1363076","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A scalable GF(2/sup m/) arithmetic unit for application in an ECC processor
This paper proposes a new architecture for an arithmetic unit (AU) for applications that operate over GF(2/sup m/), in particular elliptic curve cryptography. The AU is completely scalable enabling it to operate over any field degree without the need to reconfigure hardware. Operands are considered as a series of w-bit words, where w can be set to meet design requirements. By transferring the complexity of control to software, whilst retaining the generic functions of division and multiplication in hardware, a low area, highly flexible implementation can be attained. A proof-of concept AU was implemented and tested in FPGA. Theoretical results were calculated for scalar multiplication, which were compared to a less scalable implementation. Though the AU cannot achieve the computational speed attained by the other implementation it offers potentially large improvements when considering the area-time product and, therefore, improved efficiency.