多核cpu上三对角化的缓存高效实现和批处理

Shuhei Kudo, Toshiyuki Imamura
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引用次数: 3

摘要

本文提出了一种在多核cpu上有效实现小矩阵三对角化(TRD)的方法。三对角化是一种矩阵分解,用作特征值计算的预处理器。此外,即使在高性能计算环境中,这种小矩阵的TRD也会作为大型计算的子问题出现。为了利用最新多核cpu的大缓存,我们通过引入系统代码生成器重构了实现的所有部分,以实现性能可移植性和未来的可扩展性。系统的灵活性使我们能够结合“BLAS+X”方法,从而提高TRD算法和批处理的数据可重用性。性能结果表明,我们的系统在三种不同的多核cpu (Fujitsu SPARC64、Intel Xeon和Xeon Phi)上的性能比TRD的库实现高出近两倍(对于小矩阵来说甚至更多)。作为扩展,我们还使用系统顶部的缓存感知调度器实现了TRD的批处理执行。它不仅将n = O(100)的小矩阵的峰值性能提高了一倍,而且还显著提高了n = O(1000),这是我们的目标。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Cache-efficient implementation and batching of tridiagonalization on manycore CPUs
We herein propose an efficient implementation of tridiagonalization (TRD) for small matrices on manycore CPUs. Tridiagonalization is a matrix decomposition that is used as a preprocessor for eigenvalue computations. Further, TRD for such small matrices appears even in the HPC environment as a subproblem of large computations. To utilize the large cache memory of recent manycore CPUs, we reconstructed all parts of the implementation by introducing a systematic code generator to achieve performance portability and future extensibility. The flexibility of the system allows us to incorporate the "BLAS+X" approach, thereby improving the data reusability of the TRD algorithm and batching. The performance results indicate that our system outperforms the library implementations of TRD nearly twofold (or more for small matrices), on three different manycore CPUs: Fujitsu SPARC64, Intel Xeon, and Xeon Phi. As an extension, we also implemented the batching execution of TRD with a cache-aware scheduler on the top of our system. It not only doubles the peak performance at small matrices of n = O(100), but also improves it significantly up to n = O(1, 000), which is our target.
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