Mohammad Javad Zavarei, MohammadReza Baghbanmanesh, E. Kargaran, H. Nabovati, A. Golmakani
{"title":"采用混合cmos逻辑风格的新型全加法器单元的设计","authors":"Mohammad Javad Zavarei, MohammadReza Baghbanmanesh, E. Kargaran, H. Nabovati, A. Golmakani","doi":"10.1109/ICECS.2011.6122310","DOIUrl":null,"url":null,"abstract":"In this paper, we propose a novel 1-bit full adder using hybrid-CMOS logic style. The new full adder is based on a novel XOR-XNOR circuit that generates XOR and XNOR full-swing outputs simultaneously and outperforms its best counterpart showing 28% improvement in power-delay product (PDP). Design of proposed full adder is based on improvement in the PDP and it provides full-swing output with good driving capability. Simulations demonstrate that full adder successfully operates in the PDP compared to similar circuits.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"32","resultStr":"{\"title\":\"Design of new full adder cell using hybrid-CMOS logic style\",\"authors\":\"Mohammad Javad Zavarei, MohammadReza Baghbanmanesh, E. Kargaran, H. Nabovati, A. Golmakani\",\"doi\":\"10.1109/ICECS.2011.6122310\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we propose a novel 1-bit full adder using hybrid-CMOS logic style. The new full adder is based on a novel XOR-XNOR circuit that generates XOR and XNOR full-swing outputs simultaneously and outperforms its best counterpart showing 28% improvement in power-delay product (PDP). Design of proposed full adder is based on improvement in the PDP and it provides full-swing output with good driving capability. Simulations demonstrate that full adder successfully operates in the PDP compared to similar circuits.\",\"PeriodicalId\":251525,\"journal\":{\"name\":\"2011 18th IEEE International Conference on Electronics, Circuits, and Systems\",\"volume\":\"15 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"32\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 18th IEEE International Conference on Electronics, Circuits, and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECS.2011.6122310\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2011.6122310","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of new full adder cell using hybrid-CMOS logic style
In this paper, we propose a novel 1-bit full adder using hybrid-CMOS logic style. The new full adder is based on a novel XOR-XNOR circuit that generates XOR and XNOR full-swing outputs simultaneously and outperforms its best counterpart showing 28% improvement in power-delay product (PDP). Design of proposed full adder is based on improvement in the PDP and it provides full-swing output with good driving capability. Simulations demonstrate that full adder successfully operates in the PDP compared to similar circuits.