基于VHDL的低功耗开放核协议桥接接口分析

R. Bhakthavatchalu, G. Deepthy, S. Vidhya, V. Nisha
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引用次数: 2

摘要

片上系统(SoC)设计由于其复杂性和知识产权(IP)重用的必要性而变得具有挑战性,以缩短设计时间。一种有效的IP块间核心通信总线协议是OCP。开放核心协议(OCP)定义了唯一一个非专有的、公开许可的、以核心为中心的协议,在IP核之间具有高性能、总线无关的接口,可以减少设计时间、设计风险和制造成本,并促进SOC设计的IP核可重用性。总线桥接其他总线标准到OCP。I2C是一种简单的双向两线总线,用于高效的IC间控制。本文重点研究了基于OCP主协议和I2C从协议的总线桥的设计与实现。采用多电压设计降低功率是本文的重要特点。所开发的面向OCP和I2C的FSM在VHDL语言中实现,使用Xilinx ISE 10.1和Synopsys ASIC合成工具设计编译器进行合成。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Analysis of low power open core protocol bridge interface using VHDL
System on Chip (SoC) design is becoming challenging due to its complexity and the necessity of Intellectual Properties (IP) reuse to shorten the design time. An efficient bus protocol for the core communication between IP block is OCP. Open Core Protocol (OCP) defines the only non-proprietary, openly licensed, core centric protocol with high-performance, bus-independent interface between IP cores that reduces design time, design risk, and manufacturing costs and promote IP core reusability for SOC designs. Bus Bridge interconnects other bus standard to OCP. I2C is a simple bi-directional two wire bus for efficient inter IC control. This paper focus on the design and implementation of Bus Bridge using OCP master and I2C slave protocol. The power reduction using Multi voltage design is the important feature of the paper. The developed FSM's for OCP and I2C were implemented in VHDL and the Synthesis is done using Xilinx ISE 10.1 and Synopsys ASIC synthesis tool design compiler.
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