DNN2FPGA: Generic Design Flow to Implement DNNs on FPGAs

Deep Neural Networks (DNNs) have recently indicated a considerable advantage in many deep learning tasks such as image classification and speech recognition. However, the achievement of high-performance DNNs has accompanied an expansion in computing and memory requirements. Due to these features, the Field-Programmable Gate Arrays (FPGA) devices are ideal for deploying DNNs, and they have the required flexibility, power efficiency, and computing performance. The implementation of DNN on FPGA is usually done using a high-level language such as python, followed by a manual transformation to Hardware Description Language (HDL), and finally, the synthesis using a vendor tool. This transformation is time-consuming and requires HDL expertise, which limits the relevance of FPGAs. The paper reviews some related works, shows the proposed design flow, then the hardware implementation, and shows two case study results: A Multi-Layer Perceptron (MLP) used to solve the classical XOR problem DNN for MNIST dataset classification. Finally, we present the conclusion and future works. This paper presents a new generic design flow of implementing DNN models automatically from the high-level language to FPGA devices, which takes the model in graph presentation as input and automatically generates the FPGA’s hardware implementations.