功率平面噪声耦合到高速信号

2015 IEEE 19th Workshop on Signal and Power Integrity (SPI) Pub Date : 2015-05-10 DOI:10.1109/SAPIW.2015.7237390

F. Demuynck, L. Eichinger, V. Poisson

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引用次数: 2

摘要

在高速数字设计中，功率平面噪声是一个众所周知的信号完整性问题的来源。本文首先回顾了问题根源的基本原理。然后，我们说明了如何使用电子设计自动化(EDA)工具来分析这种现象，并提供了如何通过调整设计来减轻问题的指导。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Power plane noise coupling to high speed signals

Power plane noise is a well-known source of signal integrity (SI) issues in a high speed digital design. This paper first reviews the basic principles which are at the root of the problem. We then illustrate how electronic design automation (EDA) tools can be used to analyze the phenomenon and provide guidance on how to mitigate the issue by adjusting the design.

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2015 IEEE 19th Workshop on Signal and Power Integrity (SPI)

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