{"title":"在0.13/spl mu/m CMOS中的1.2V 10b 20MSample/s非二进制逐次逼近ADC","authors":"Franz Kuttner","doi":"10.1109/ISSCC.2002.992993","DOIUrl":null,"url":null,"abstract":"A successive-approximation ADC with non-binary code achieves 55dB SNR at sampling frequencies up to 20MHz. The converter, with on-chip driver for analog input and reference input, measures 0.08mm/sup 2/ in a standard 0.13/spl mu/m CMOS process and consumes 12mW from a single 1.2V supply.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"99","resultStr":"{\"title\":\"A 1.2V 10b 20MSample/s non-binary successive approximation ADC in 0.13/spl mu/m CMOS\",\"authors\":\"Franz Kuttner\",\"doi\":\"10.1109/ISSCC.2002.992993\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A successive-approximation ADC with non-binary code achieves 55dB SNR at sampling frequencies up to 20MHz. The converter, with on-chip driver for analog input and reference input, measures 0.08mm/sup 2/ in a standard 0.13/spl mu/m CMOS process and consumes 12mW from a single 1.2V supply.\",\"PeriodicalId\":423674,\"journal\":{\"name\":\"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)\",\"volume\":\"29 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"99\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2002.992993\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2002.992993","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 1.2V 10b 20MSample/s non-binary successive approximation ADC in 0.13/spl mu/m CMOS
A successive-approximation ADC with non-binary code achieves 55dB SNR at sampling frequencies up to 20MHz. The converter, with on-chip driver for analog input and reference input, measures 0.08mm/sup 2/ in a standard 0.13/spl mu/m CMOS process and consumes 12mW from a single 1.2V supply.