大型末级缓存的性能建模与表征

Parijat Dube, M. Tsao, Li Zhang, A. Bivens
{"title":"大型末级缓存的性能建模与表征","authors":"Parijat Dube, M. Tsao, Li Zhang, A. Bivens","doi":"10.1109/ISPASS.2012.6189215","DOIUrl":null,"url":null,"abstract":"Different workloads exhibit different memory footprint and have different dependency on the size and configuration of the memory hierarchy. To quantify the performance implication of various memory system architectures and attributes one needs to understand the program behavior of an application/workload and its use of the memory subsystem. One such architecture studied in this paper is where multiple memory technologies are integrated into the memory system with one (typically the faster, more expensive technology) acting as a large cache for the other (typically a slower, cheaper technology). We develop a large cache prototype to study the performance of different applications and their sensitivity to different architecture parameters. The prototype measures different metrics associated with a cache performance which are in turn used to characterize the performance implications of such a memory architecture on different workloads and the dependency on different configuration parameters.","PeriodicalId":278764,"journal":{"name":"2012 IEEE 20th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Performance Modeling and Characterization of Large Last Level Caches\",\"authors\":\"Parijat Dube, M. Tsao, Li Zhang, A. Bivens\",\"doi\":\"10.1109/ISPASS.2012.6189215\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Different workloads exhibit different memory footprint and have different dependency on the size and configuration of the memory hierarchy. To quantify the performance implication of various memory system architectures and attributes one needs to understand the program behavior of an application/workload and its use of the memory subsystem. One such architecture studied in this paper is where multiple memory technologies are integrated into the memory system with one (typically the faster, more expensive technology) acting as a large cache for the other (typically a slower, cheaper technology). We develop a large cache prototype to study the performance of different applications and their sensitivity to different architecture parameters. The prototype measures different metrics associated with a cache performance which are in turn used to characterize the performance implications of such a memory architecture on different workloads and the dependency on different configuration parameters.\",\"PeriodicalId\":278764,\"journal\":{\"name\":\"2012 IEEE 20th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems\",\"volume\":\"39 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-04-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 IEEE 20th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISPASS.2012.6189215\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE 20th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPASS.2012.6189215","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

摘要

不同的工作负载表现出不同的内存占用,并且对内存层次结构的大小和配置有不同的依赖关系。要量化各种内存系统架构和属性的性能含义,需要了解应用程序/工作负载的程序行为及其对内存子系统的使用。本文研究的一种架构是将多种存储技术集成到存储系统中,其中一种(通常是更快、更昂贵的技术)充当另一种(通常是更慢、更便宜的技术)的大缓存。我们开发了一个大型缓存原型来研究不同应用程序的性能及其对不同架构参数的敏感性。原型测量与缓存性能相关的不同指标,这些指标反过来用于描述这种内存架构在不同工作负载上的性能含义以及对不同配置参数的依赖性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Performance Modeling and Characterization of Large Last Level Caches
Different workloads exhibit different memory footprint and have different dependency on the size and configuration of the memory hierarchy. To quantify the performance implication of various memory system architectures and attributes one needs to understand the program behavior of an application/workload and its use of the memory subsystem. One such architecture studied in this paper is where multiple memory technologies are integrated into the memory system with one (typically the faster, more expensive technology) acting as a large cache for the other (typically a slower, cheaper technology). We develop a large cache prototype to study the performance of different applications and their sensitivity to different architecture parameters. The prototype measures different metrics associated with a cache performance which are in turn used to characterize the performance implications of such a memory architecture on different workloads and the dependency on different configuration parameters.
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