A 10-fJ/bit/dB half-rate equalizer with charge-average switched-capacitor summation technique

This paper presents a 6 Gb/s low-power half-rate equalizer. Compared with the current steering summation circuits, the proposed charge-average switched-capacitor equalizer achieves good energy and area efficiency, and thus is suitable for multi-lane applications. The proposed architecture are majorly constructed by switched-capacitor and digital circuitries, it is hence suitable for advanced manufacturing process. The proof-of-concept prototype was fabricated in TSMC 0.18 um CMOS technology. It occupies 0.0034 mm2 area and the figure of merit is 10 fJ/bit/dB while operating at a bit-error-rate <; 10-12 for 6 Gb/s data passed over a 100 cm FR4 PCB channel with 23.2 dB channel loss at 3 GHz.