{"title":"一种基于数字周期合成的0.3 ~ 8.5 ghz频率合成器","authors":"Tapio Rapinoja, K. Stadius, J. Ryynänen","doi":"10.1109/ESSCIRC.2013.6649116","DOIUrl":null,"url":null,"abstract":"This paper presents a wide-band digital frequency synthesizer based on digital period synthesis (DPS). As a direct frequency synthesis method, the DPS architecture achieves inherently wide operational band, high frequency resolution and instantaneous settling. The frequency synthesizer, including reference delay-locked loop (DLL), DPS unit, and frequency multiplying DLL, was implemented in a 65-nm CMOS process and it occupies an active area of 0.3 mm2. The implemented frequency synthesizer covers a frequency range from 0.3 GHz to 8.5 GHz with 1 Hz frequency resolution, 550 fs integrated jitter, and 0.9 μs settling time.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 0.3-to-8.5GHz frequency synthesizer based on digital period synthesis\",\"authors\":\"Tapio Rapinoja, K. Stadius, J. Ryynänen\",\"doi\":\"10.1109/ESSCIRC.2013.6649116\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a wide-band digital frequency synthesizer based on digital period synthesis (DPS). As a direct frequency synthesis method, the DPS architecture achieves inherently wide operational band, high frequency resolution and instantaneous settling. The frequency synthesizer, including reference delay-locked loop (DLL), DPS unit, and frequency multiplying DLL, was implemented in a 65-nm CMOS process and it occupies an active area of 0.3 mm2. The implemented frequency synthesizer covers a frequency range from 0.3 GHz to 8.5 GHz with 1 Hz frequency resolution, 550 fs integrated jitter, and 0.9 μs settling time.\",\"PeriodicalId\":183620,\"journal\":{\"name\":\"2013 Proceedings of the ESSCIRC (ESSCIRC)\",\"volume\":\"29 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-10-31\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 Proceedings of the ESSCIRC (ESSCIRC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2013.6649116\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 Proceedings of the ESSCIRC (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2013.6649116","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 0.3-to-8.5GHz frequency synthesizer based on digital period synthesis
This paper presents a wide-band digital frequency synthesizer based on digital period synthesis (DPS). As a direct frequency synthesis method, the DPS architecture achieves inherently wide operational band, high frequency resolution and instantaneous settling. The frequency synthesizer, including reference delay-locked loop (DLL), DPS unit, and frequency multiplying DLL, was implemented in a 65-nm CMOS process and it occupies an active area of 0.3 mm2. The implemented frequency synthesizer covers a frequency range from 0.3 GHz to 8.5 GHz with 1 Hz frequency resolution, 550 fs integrated jitter, and 0.9 μs settling time.