低功率数字锁相环的设计与分析

2016 8th International Conference on Computational Intelligence and Communication Networks (CICN) Pub Date : 2016-12-01 DOI:10.1109/CICN.2016.60

D. Bhati, Balwinder Singh

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引用次数: 6

摘要

提出了一种新的数字锁相环结构。该架构包括以下模块:低功率相位和频率检测器(PFD)在90nm技术节点上消耗19.7nw，时间到数字转换器(TDC)减少输入信号的相位误差，数字控制器振荡器(DCO)在深亚微米CMOS工艺中合成射频频率。所有模块都集成在一起，以减少锁定范围和最小化抖动。

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Design and Analysis of a Low Power Digital Phase Locked Loop

This paper presents a novel architecture for digital phase locked loop. This architecture includes following modules: Low power phase and frequency detector (PFD) consumed 19.7nw at 90nm technology node, time to digital converter (TDC) to reduce error in phase of the input signal, digitally controller oscillator (DCO) to synthesize RF frequencies in deep submicron CMOS process. All modules are integrated in order to reduce locking range and to minimize jitter.

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来源期刊

2016 8th International Conference on Computational Intelligence and Communication Networks (CICN)

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