{"title":"在(p,q)计数器实现中使用1- of-n码","authors":"R. McIlhenny, M. Ercegovac","doi":"10.1109/ACSSC.1996.600854","DOIUrl":null,"url":null,"abstract":"A new approach for implementing (p,q) counters is introduced, using 1-out-of-n code modules. The circuits were implemented in 1.2 /spl mu/m CMOS technology, and simulated using HSpice to measure the cost, delay, and average power consumption. Through simulation, the new method is shown to yield an average 19% reduction in critical delay, and an average 30% reduction in average power consumption, with the tradeoff of a 38% increase in average cost.","PeriodicalId":270729,"journal":{"name":"Conference Record of The Thirtieth Asilomar Conference on Signals, Systems and Computers","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"On using 1-out-of-n codes for (p,q) counter implementations\",\"authors\":\"R. McIlhenny, M. Ercegovac\",\"doi\":\"10.1109/ACSSC.1996.600854\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new approach for implementing (p,q) counters is introduced, using 1-out-of-n code modules. The circuits were implemented in 1.2 /spl mu/m CMOS technology, and simulated using HSpice to measure the cost, delay, and average power consumption. Through simulation, the new method is shown to yield an average 19% reduction in critical delay, and an average 30% reduction in average power consumption, with the tradeoff of a 38% increase in average cost.\",\"PeriodicalId\":270729,\"journal\":{\"name\":\"Conference Record of The Thirtieth Asilomar Conference on Signals, Systems and Computers\",\"volume\":\"4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-11-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Conference Record of The Thirtieth Asilomar Conference on Signals, Systems and Computers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ACSSC.1996.600854\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Conference Record of The Thirtieth Asilomar Conference on Signals, Systems and Computers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ACSSC.1996.600854","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
On using 1-out-of-n codes for (p,q) counter implementations
A new approach for implementing (p,q) counters is introduced, using 1-out-of-n code modules. The circuits were implemented in 1.2 /spl mu/m CMOS technology, and simulated using HSpice to measure the cost, delay, and average power consumption. Through simulation, the new method is shown to yield an average 19% reduction in critical delay, and an average 30% reduction in average power consumption, with the tradeoff of a 38% increase in average cost.
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