Design and implementation of a fast interrupt system based on RISC-V

Interrupt technology is a key technology for processors to respond to external events and plays an important role in the embedded field. The open source RISC-V architecture defines a complete set of interrupt mechanisms with hardware definitions that do not support interrupt nesting in embedded systems that only support machine mode, and software support for interrupt nesting adds additional time overhead. This paper is based on the interrupt mechanism defined by RISC-V, using a state machine to control the global interrupt enablement of the processor to support interrupt nesting, and to save the site and restore the site through hardware stacking and out-stacking to avoid the time consumption caused by the software level; a dedicated entry point for interrupt service program jumps further speeds up the response. In this paper, we design and implement a fast interrupt system using Hummingbird E203, an open source kernel defined by standard RISC-V, as an experimental platform. Simulation verification and comprehensive implementation on FPGA platform show that compared to the interrupt handling process of Hummingbird E203, using a small amount of hardware resource consumption, the response speed is improved by 1/4, providing better real-time performance and flexibility in embedded applications.