Verilog-A Modeling of Junction-less MOSFET in Sub- Threshold Regime for Ultra Low-Power Application

A VERILOG A model of Bulk Current of Long- Channel Double-Gate Junctionless MOSFET is presented here. The basic physics of the model is briefly along with a simple flow chart. Proposed model data has been verified with the device models reported in the recent literatures. The model file is used to design and implement the Inverter, NAND/NOR circuits. Power dissipations and the delay of the double gate junctionless MOSFET based Inverter, NAND/NOR gates have been measured and compared with the conventional bulk MOSFET of similar dimensions. From the simulation data it is obvious that the junctionless MOSFET based digital logic circuits consume less power and higher speed compared to the conventional MOSFET based circuitry. The proposed model can be used to predict the power and delay of complex logic circuits based on the non-planner MOSFETs.