10b 200MS/s 0.82mW SAR ADC, 40nm CMOS

2013 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2013-12-23 DOI:10.1109/ASSCC.2013.6691039

Guan-Ying Huang, Soon-Jyh Chang, Ying-Zu Lin, Chun-Cheng Liu, Chun-Po Huang

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引用次数: 21

摘要

本文报道了一种连续逼近模数转换器(ADC)，它结合了旁路窗和直接开关技术来容忍不完全稳定误差和降低控制逻辑延迟。一个小的单位电容器电池减少了功耗和沉淀时间。10位原型机采用40nm CMOS工艺制造。在200 MS/s和0.9 v电源下，该ADC功耗为0.82 mW, SNDR为57.16 dB, FOM为13.9 fJ/转换步长。

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A 10b 200MS/s 0.82mW SAR ADC in 40nm CMOS

This paper reports a successive-approximation analog-to-digital converter (ADC) which combines the bypass window and direct switching technique to tolerate the incomplete settling error and reduce the control logic delay. A small unit capacitor cell reduces the power consumption and settling time. The 10-bit prototype is fabricated in a 40nm CMOS process. At 200 MS/s and 0.9-V supply, this ADC consumes 0.82 mW and achieves an SNDR of 57.16 dB, resulting in an FOM of 13.9 fJ/Conversion-step.

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2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)

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