MedianPipes: An FPGA based Highly Pipelined and Scalable Technique for Median Filtering (Abstract Only)

We propose MedianPipes, a novel, FPGA based, highly pipelined and scalable architecture for median filtering. Median filters and its variants are widely used for noise suppression in image processing. All variants of median filter depend on the computation of median values. MedianPipe is a highly pipelined architecture and hence an ideal fit for FPGAs. It does not make any assumptions about the image to fit on the on-chip memory. Instead, the image is assumed to be streamed-in in the form of image slices. Multiple MedianPipe modules are used depending on the size of image slice and hence the overall hardware complexity of proposed technique scales linearly with image-slice size. The architecture for MedianPipe is based on the principle of merge sort and uses a median window of size 3 x 3. It consists of two stepped sorting process: The first step is to sort the pixels within each row of median window to get sorted rows. This sorting is done using a single comparator over multiple clock cycles. The sorted rows are saved in block memory based First-In-First-Out (FIFO) memory and reused to calculate the medians corresponding to three median windows. The second step is to merge these sorted rows to find the median using a merger block. The merger block consists of three comparators and read out a single value every cycle once the pipeline is filled. Without loss of generality, the pixels of an image slice are assumed to be read in a column major format. All the median values within the column of the image slice can be computed in parallel using multiple MedianPipes. The computation of median values in the following column is delayed by a clock cycle. Hardware resources scale linearly by varying the pixel sizes and number of MedianPipes. The pixel rate achieved for various pixel sizes is well above 124 MHz which is the standard for 1080p High-Definition.