{"title":"动态阈值绝缘体上硅CMOS逆变器的功耗研究","authors":"W. Jin, Philip C. H. Chan, M. Chan","doi":"10.1109/LPE.1997.621292","DOIUrl":null,"url":null,"abstract":"The leakage current due to the parasitic PN junction diodes in SOI DTMOS (Dynamic threshold voltage MOSFET) inverter is reported. The additional power dissipation in DTMOS inverter due to the diodes is quantified through an analytical model and verified by MEDICI simulation. Power dissipation between conventional SOI CMOS and SOI DTMOS inverters is compared.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"On the power dissipation in dynamic threshold silicon-on-insulator CMOS inverter\",\"authors\":\"W. Jin, Philip C. H. Chan, M. Chan\",\"doi\":\"10.1109/LPE.1997.621292\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The leakage current due to the parasitic PN junction diodes in SOI DTMOS (Dynamic threshold voltage MOSFET) inverter is reported. The additional power dissipation in DTMOS inverter due to the diodes is quantified through an analytical model and verified by MEDICI simulation. Power dissipation between conventional SOI CMOS and SOI DTMOS inverters is compared.\",\"PeriodicalId\":334688,\"journal\":{\"name\":\"Proceedings of 1997 International Symposium on Low Power Electronics and Design\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 1997 International Symposium on Low Power Electronics and Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/LPE.1997.621292\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/LPE.1997.621292","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
摘要
报道了SOI动态阈值电压MOSFET (Dynamic threshold voltage MOSFET)逆变器中寄生PN结二极管的漏电流。通过分析模型量化了二极管在DTMOS逆变器中的附加功耗,并通过MEDICI仿真进行了验证。比较了传统SOI CMOS和SOI DTMOS逆变器的功耗。
On the power dissipation in dynamic threshold silicon-on-insulator CMOS inverter
The leakage current due to the parasitic PN junction diodes in SOI DTMOS (Dynamic threshold voltage MOSFET) inverter is reported. The additional power dissipation in DTMOS inverter due to the diodes is quantified through an analytical model and verified by MEDICI simulation. Power dissipation between conventional SOI CMOS and SOI DTMOS inverters is compared.