明星倍增器

Conference Record of The Twenty-Ninth Asilomar Conference on Signals, Systems and Computers Pub Date : 1995-10-30 DOI:10.1109/ACSSC.1995.540619

E. de Angel, A. Chowdhury, E. Swartzlander

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引用次数: 0

摘要

本文介绍了一种新型高速并行乘法器的结构。一种基于双环结构和改进的booth(1951)算法的新架构在显著减少硬件的情况下实现了高速乘法。该32 × 32位星型乘法器采用0.6 /spl mu/m CMOS工艺设计，乘法时间为17.5 ns。

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The star multiplier

This paper presents the architecture of a new high speed parallel multiplier. A novel architecture based on two ring structures and the modified-Booth (1951) algorithm achieve high speed multiplications with a significant reduction in hardware. The 32 by 32 bit star multiplier has been designed in a 0.6 /spl mu/m CMOS technology and presents a multiplication time of 17.5 ns.

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Conference Record of The Twenty-Ninth Asilomar Conference on Signals, Systems and Computers

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