Analysis on loop area trace radiated emissions from decoupling capacitor placement on printed circuit boards

This paper presents, with a solid conclusion, practical, hands-on applied EMC information for engineers that can be put to immediate use without relying on the mathematics of Maxwell's equations. An examination is made to determine if the physical placement of decoupling capacitors makes a significant difference in the development and propagation of radiated emissions from a printed circuit board (PCB) when used with actual, high-speed components. The focus is on what happens on both the top and bottom layers of a PCB, regardless of whether the board is single-sided, double-sided or multilayer. This paper complements existing research that investigates decoupling using simulation. Correlation between simulation and actual results is supported in this paper. A problem with simulation is that results calculated sometimes cannot take into consideration common-mode RF energy developed by components switching multiple outputs under maximum capacitive load, consuming a large amount of inrush current or impulse currents from switching cross-conduction. Common-mode energy cannot always be efficiently simulated at this time, thus causing the possibility of inaccurate assumptions regarding anticipated radiated emissions from a PCB layout. Behavioral models used for simulation are usually (theoretically) perfect and may not represent actual design parameters due to parasitics and other electromagnetic effects that cannot be easily calculated or anticipated. RF energy is developed due to digital components switching logic states. A voltage gradient on the power and ground planes between components causes common-mode EMI to be observed on interconnects and other radiating structures. Decoupling capacitors are provided to minimize voltage gradients, along with minimizing RF switching energy injected into the power distribution network and distributed throughout the entire PCB. The magnitude of radiated energy, related to decoupling capacitors is investigated in this paper, based on the physical location to digital components. In addition, common engineering problems in determining an optimal decoupling capacitor value are presented, with regard to both time and frequency domain analysis.