并行乘法器中最后加法器的设计策略

P. Stelling, V. Oklobdzija
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引用次数: 18

摘要

在本文中,我们解决了当比特到达时间是任意的(但事先已知的)时,添加两个n位数字的问题。特别是,我们解决了这个问题的一个简化版本,其中两个加数的i/sup /有效位的输入到达时间是相同的,并且到达时间t/下标i/具有如下形式的概况:t/下标0//spl les/t/下标1//spl les/…/spl les/t/sub k/=t/sub k+1/=…=t/下标p/>t/下标p+1//spl ges/…/spl ges/t/sub n-1/。这个轮廓很重要,因为它与在最终加法器中求和之前并行乘法器中减少的部分乘积的信号到达时间轮廓相匹配。在本文中,我们提出了一种特定于到达时间轮廓的设计策略,该轮廓是通过优化应用V.G. Oklobdzija等人(1995)提出的三维方法构建的部分积约简树生成的。此策略可用于获得与上述形式匹配的任何到达时间配置文件的加法器,以及允许输入时间发生更大变化的广泛类别的到达时间配置文件。最后,我们表明,我们的设计明显优于均匀信号到达配置文件的标准加法器设计,产生更快的加法器(对于这些配置文件)也更简单,使用更少的门。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design strategies for the final adder in a parallel multiplier
In this paper we address the problem of adding two n-bit numbers when the bit arrival times are arbitrary (but known in advance). In particular we address a simplified version of the problem where the input arrival times for the i/sup th/ significant bits of both addends are the same, and the arrival times t/sub i/ have a profile of the form: t/sub 0//spl les/t/sub 1//spl les/.../spl les/t/sub k/=t/sub k+1/=...=t/sub p/>t/sub p+1//spl ges/.../spl ges/t/sub n-1/. This profile is important because it matches the signal arrival time profile of the reduced partial products in a parallel multiplier before they are summed in the final adder. In this paper we present a design strategy specific to arrival time profiles generated by partial product reduction trees constructed by optimal application of the Three Dimensional Method presented by V.G. Oklobdzija et al. (1995). This strategy can be used to obtain adders for any arrival time profile that matches the above form, as well as a broad class of arrival time profiles where even greater variation in the input times is allowed. Finally, we show that our designs significantly outperform the standard adder designs for the uniform signal arrival profile, yielding faster adders that (for these profiles) are also simpler and use fewer gates.
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