A Low-Power RF Programmable Frequency Divider

Since the popularization of 5G communications in 2019, the requirements of wireless communication related to data transmission have become higher and higher. As a universal module in the chip circuit, the phase-locked-loop (PLL) is widely used in the fields of wireless radio frequency communication and high-performance digital circuits, providing accurate clocks for various high-performance and high-speed circuits. Frequency divider as an important module of PLL, its performance will directly affect the whole PLL noise. Based on 0.18μm CMOS technology, a low-power RF programmable frequency divider with a frequency division ratio of 9~767, a step of 1, and a power consumption of no more than 1.68mW at 2GHz is implemented in this paper.