用于高性能处理器的低成本、高质量嵌入式阵列DFT技术

Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06) Pub Date : 2006-01-17 DOI:10.1109/DELTA.2006.5

Z. Bao, S. Kumar, David M. Wu, Vimal K. Natarajan, Mike Lin

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引用次数: 0

摘要

本文介绍了一种低成本、高质量的阵列DFT技术，该技术可将整体制造测试时间节省50%。该技术通过并行的直接存取测试接口将可编程的片上测试生成引擎集成到直接存取测试(DAT)控制器中。它可以用来测试不同类型的嵌入式阵列在系统速度。该方法已在Intel/spl reg/高性能微处理器上得到验证。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A low cost, high quality embedded array DFT technique for high performance processors

This paper describes a low cost, high quality array DFT technique that will save overall manufacturing test time by /spl sim/50%. This technique integrates a programmable on-die test generation engine into the direct access test (DAT) controller via the parallel DAT interfaces. It can be used to test different types of embedded arrays at system speed. It has been validated on an Intel/spl reg/ high performance microprocessor design.

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Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)

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