Inkjet-printed WS2 and MoSe2 transistors with edge-FET architecture and near-vertical electronic transport

Two dimensional (2D) semiconductors combine the advantages of both oxide and organic semiconductor world, namely, high carrier mobility, environmental stability, as well as room temperature processability, flexibility and the availability of both high carrier mobility n- and p-type semiconductor variants. However, for their realization in flexible, wearable electronics, high throughput solution processing techniques, such as printing is essential. However, when solution processed, the performance of the devices deteriorates substantially due to huge inter-flake resistance. To overcome this challenge, here we propose and demonstrate an unconventional thin film transistor (TFT) device architecture which can circumvent the shortcoming of large inter-flake resistance by transforming the TFTs into predominantly intra-flake transport edge-FETs. Using this edge-FET device architecture, here we present TFTs printed from chemically exfoliated WS2 and MoSe2 inks, with 106 µA/µm and 25 µA/µm width-normalized, On-state current density, respectively. On the other hand, the maximum On-Off ratio observed in these printed TFTs have also been large, as high as 107 has been recorded, which is surely a rarity in solution-processed 2D electronics. In addition, a tunable channel capacitance mediated subthermionic transport with minimum subthreshold slope of 36 mV/dec has also been observed.