Efficient reverse converters designs for RNS based digital signal processing systems

Residue Number System based signal processing is an efficient alternative to the conventional methods due to its small data size and parallel arithmetic operations. This paper presents the designs of the RNS to binary reverse converter, which is a critical component in a RNS based system. Different RNS modulo adders required to implement the reverse converter for the {2k-1, 2k, 2k+1} moduli set are evaluated. Their performances are then compared against each other. FPGA synthesis results are also presented to demonstrate the performance efficiency of the different designs.