45纳米技术中32位加法器的泄漏分析

2017 IEEE 7th International Advance Computing Conference (IACC) Pub Date : 1900-01-01 DOI:10.1109/IACC.2017.0092

M. Ahmad, K. Manjunathachari, K. Lalkishore

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引用次数: 1

摘要

本文利用现有的全加法器和拟制加法器设计了32位加法器。与所有现有的基于15晶体管的32位加法器和基于13晶体管的32位加法器相比，所有32个全加法器的平均泄漏和平均功耗都很小。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Analysis of Leakage in 32-Bit Adders in 45 nm Technology

In this paper 32 bit adders are designed usingexisting full adders and proposed adders. Average leakage andaverage power consumed in all 32 full adders is small comparedto all existing, proposed 15 transistor based 32 bit adder andproposed 13 transistor based 32 bit adder.

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来源期刊

2017 IEEE 7th International Advance Computing Conference (IACC)

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