了解并发错误检测超标量微体系结构的性能

Jared C. Smolens, Jangwoo Kim, J. Hoe, B. Falsafi
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引用次数: 3

摘要

可以修改超标量无序微体系结构,以支持程序作为两个并发线程的冗余执行,以进行软错误检测。但是,由于整个数据路径对资源的争用增加,冗余执行带来的额外工作负载会导致性能损失。我们提出了影响这些设计性能的四个关键参数,即1)发布和功能单元带宽,2)发布队列和重排序缓冲区容量,3)解码和退役带宽,以及4)冗余线程瞬时资源需求之间的耦合。然后,我们调查了现有的并发错误检测超标量微体系结构的工作,并根据四个因素对这些建议进行了评估
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Understanding the performance of concurrent error detecting superscalar microarchitectures
Superscalar out-of-order micro architectures can be modified to support redundant execution of a program as two concurrent threads for soft-error detection. However, the extra workload from redundant execution incurs a performance penalty due to increased contention for resources throughout the datapath. We present four key parameters that affect performance of these designs, namely 1) issue and functional unit bandwidth, 2) issue queue and reorder buffer capacity, 3) decode and retirement bandwidth, and 4) coupling between redundant threads' instantaneous resource requirements. We then survey existing work in concurrent error detecting superscalar micro architectures and evaluate these proposals with respect to the four factors
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