65nm BEOL蚀刻问题的研究

2008 9th International Conference on Solid-State and Integrated-Circuit Technology Pub Date : 2008-12-30 DOI:10.1109/ICSICT.2008.4734747

Linlin Zhao, Manhua Shen, Qiu-hua Han, Hai-yang Zhang, Shih-Mou Chang

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引用次数: 3

摘要

65nm BEOL沟槽蚀刻容易遭受边际PR问题。同时满足金属电阻(Rs)和击穿电压(VBD)的要求是刻蚀工艺面临的巨大挑战。通孔底部的铜表面状况也是蚀刻工艺的一个重要问题。在本文中，我们提出了在65nm沟槽蚀刻工艺中发生的几个电气参数问题，如Rs，通阻(Rc)和VBD。并从改善晶圆内线边缘粗糙度(LER)、晶圆内临界尺寸均匀度(CDU)和通孔底界面条件等方面探讨了上述问题的可行解决方案和相关蚀刻机理。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A study of 65nm BEOL trench etch issues

65 nm BEOL trench etch is apt to suffer the marginal PR issue. It is a big challenge for trench etch process to simultaneously satisfy the requirements for both metal resistance (Rs) and breakdown Voltage (VBD). The copper surface condition of via bottom is a big concern of trench etch process as well. In this paper, we present several electrical parameter issues that occurred at 65 nm trench etch process such as Rs, via resistance (Rc) and VBD. The feasible solutions and related etching mechanisms are also addressed for the above issues from the point view of the improvement of line-edge roughness (LER), within wafer AEI CDU (critical dimension uniformity) and interface conditions of via-bottom.

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2008 9th International Conference on Solid-State and Integrated-Circuit Technology

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